This disclosure relates to display driver circuitry to generate an efficient timing signal by precharging to ground before transitioning between periods of positive voltage and negative voltage.
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present techniques, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Electronic displays appear in many electronic devices. One type of electronic display, known as a liquid crystal display (LCD), modulates light passing through pixels of various colors using a liquid crystal material. By programming the pixels to display different colors, images are generated on the display. To do so, display driver circuitry provides a gate clock signal to activate a row of pixels. While the pixels are activated, the display driver circuitry may program the pixels to display particular colors. Specifically, the display driver circuitry may receive multiplexed image data (e.g., a single signal of red, green, and blue (RGB) image data). Demultiplexers having switches clocked to demultiplexer timing signals then demultiplex the image data into separate signals of different colors (e.g., separate red, green, and blue signals). The display driver circuitry provides these demultiplexed image signals to the pixels while the pixels remain activated by the gate clock signal. After the pixels have been programmed, the gate clock signal deactivates the pixels.
The various timing signals used by the display driver circuitry may have periods of positive voltage and periods of negative voltage. In general, the switches and/or gates that receive the timing signals may be activated during positive voltage periods and deactivated during negative voltage periods, though this arrangement may be reversed. In either case, a positive voltage supply provides positive charge to cause the timing signal to reach a positive voltage, and a negative voltage supply provides negative charge to cause the timing signal to reach a negative voltage. Repeatedly and alternatingly providing the positive and negative charges to generate the timing signals used by the display driver circuitry may consume a substantial amount of power.
Moreover, the rise and fall transition time properties (e.g., slew rate) of these timing signals (e.g., the gate clock signals) may influence and affect channel charge distribution on the row of pixels being activated or deactivated. In some cases, a relatively rapid slew rate of the gate clock signals may cause certain visual artifacts, such as flicker, to occur more frequently and/or more severely. On the other hand, a slower slew rate may reduce some visual artifacts. As such, it may be desirable to design and provide an LCD display that can regulate the slew rate of gate clock signals, while also reducing the amount of power consumed by these signals.